exception - Is cache miss a kind of interrupt/fault -

we know page miss in memory bring page fault, , page handler must load page physical memory. here wonder whether miss in cache system fault? if not, what's difference between memory fault , cache fault? lot.

by "cache fault" mean cache miss in l1/l2/l3 caches of processor? if so, no, not generate fault, @ least on every processor architecture i've ever heard of.

the reason page fault requires software intervention decide whether access invalid, whether access page swapped out disk, etc. in contrast, cache miss can definition handled processor - since didn't cause page fault, data must stored in main memory or lower-level cache, directly accessible processor. processor mechanically translate address of memory being accessed virtual physical , asks lower-level cache or main memory data.

the same idea applies simultaneous multiprocessors, cache line might invalidated 1 core writes it, though core has stored in cache. processor defines own coherency protocol ensure stale copy not read, either forcing core invalid cache line refresh lower-level cache, or requiring watch shared write bus processors can see values being written to.