Why do I get an "Incompatible types at assignment" error in verilog? -

i have following verilog code, why "incompatible types @ assignment"-error assignment "pwmdata = 4'b1000;"? got error in active-hdl 9.2.

module pwmtestbench;  parameter datawidth = 4;  reg clock, reset, pwmdata[3:0], loadpwmdata; wire pwmout;  pwm #(.datawidth(datawidth)) pwm ( .clk(clock), .reset(reset), .data(pwmdata), .load(loadpwmdata), .out(pwmout) );  initial begin     clock = 1'b1;     reset = 1'b1;     loadpwmdata = 1'b0; end  begin     #1 clock = !clock; end  initial begin     #1   pwmdata = 4'b1000;     // # error: vcp2852 pwm_tb.v : (29, 1): incompatible types @ assignment: .pwmdata<reg[3:0]> <- 4'b1000<[3:0]bit>.     #1   loadpwmdata = 1'b1;     #2   loadpwmdata = 1'b0;     #1   reset = 1'b0;     #512 $finish; end  endmodule 

pwmdata[3:0] defines 4-element array of 1-bit entries.

if want create 4-bit register (this not same 4x 1-bit array), range goes on other side:

reg [3:0] pwmdata;