encryption - Implementation of AES algorithm using Systolic architecture -


i need generate vlsi systolic array implement aes encryption algorithm key length of 128 bits. following possible ways :

  1. systolic key expansion
  2. systolic in mixcolumn
  3. systolic on-the-fly calculation of s-box

for option #3, referring this paper. figure 2.1 paper gives steps calculating multiplicative inverse, first step in s-box calculation. trying convert diagram systolic array, haven't reached concrete solution until now.

i referring this paper convert cyclic algorithm systolic one. however, not able convert operations involved in aes encryption systolic structure. give me pointers on how approach problem?


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