vhdl - Verilog instantiation error -

i'm having issue calling module jk flip flop. our project make state machine, , logic correct, i'm getting error says "vhdl module instantiation error: can not connect instance ports both error , name"

the error on line 67, first instantiation of jk_ff

edit: i'm assuming problem has register, given http://quartushelp.altera.com/11.1/mergedprojects/msgs/msgs/evrfx_veri_not_a_structural_net_expression.htm

but i'm not sure how fix error.

//project 2 "main"  module project2(q3, q2, q1, q0, w, z0, z1, clk, rst, enable); //honestly not sure if need q or not reg q0,q1,q2,q3; input enable, w, clk, rst; output q0,q1,q2,q3,z0,z1;  initial begin //k3 <= 1'b1; // k3 = 1 end  and(newclock, clk, enable); // ned clock  //now assignments i'm guessing not(wnot, w); not(q3not, q3); not(q2not, q2); not(q1not, q1); not(q0not, q0);  // j0 assignment and(j0temp,w,q3not,q2not,q1not);  and(j0temp1,wnot,q2); and(j0temp2,wnot,q1); or(j0,j0temp, j0temp1, j0temp2);  // k0 assignment and(k0temp,q3not,q2not); or(k0,wnot,q1, k0temp);  //j1 assignment and(j1temp, wnot,q3not,q2not,q1not,q0not); and(j1temp1,w,q2); and(j1temp2,w,q0); or(j1,q3, j1temp, j1temp1, j1temp2);  //k1 assignments and(k1temp,w,q1); and(k1temp1,q2,q0); and(k1temp2,q3not,q2not,q1,q0not); or(k1,k1temp,k1temp1,k1temp2);  //j2 assignments and(j2temp,wnot,q0); and(j2temp1,w,q1); and(j2temp2,wnot,q3); or(j2, j2temp,j2temp1,j2temp2);  //k2 assignments or(k2,wnot,q1);  //j3 assignments and(j3,wnot,q2,q1,q0);  //z0 assignments and(z0temp,wnot,q0not,q2); and(z0temp1,wnot,q1,q2); or(z0,z0temp,z0temp1);  //z1 assignments and(z1temp, wnot,q2); and(z1temp1,wnot,q1,q0not); and(z1temp2,q2,q1); or(z1, z1temp, z1temp1, z1temp2);  //instantiate flip flops jk_ff y0(.j(j0),.k(k0),.clk(newclock), .rst(rst), .q(q0), .qnot(q0not)); jk_ff y1(.j(j1),.k(k1),.clk(newclock), .rst(rst), .q(q1), .qnot(q1not)); jk_ff y2(j2,k2,newclock, rst, q2, q2not); jk_ff y3(j3,k3,newclock, rst, q3, q3not);    endmodule  //asynchronous reset jk flip flop module module jk_ff(j,k,clk,rst,q, qnot); input j,k,clk,rst; output q; // not sure or if used output qnot; reg    q; reg    qnot;  @(negedge clk or negedge rst)          if(rst)begin         q <= 0;         qnot <= 1;         end         else if(~j && k) begin         q <= 0;         qnot <= 1;         end         else if(~j && ~k) begin         q <= q;         qnot <= qnot;         end         else if(j && ~k) begin         q <= 1;         qnot <= 0;         end         else if(j && k) begin         q <= qnot;         qnot <= q;         end  endmodule 

somewhere in ieee std 1364 states net , variable declarations must appear after post declarations. should somewhere in data type section. i'll update answer if find reference.

easy fix: move line 4 reg q0,q1,q2,q3; below output q0,q1,q2,q3,z0,z1;.

personally prefer using port declaration style introduced in ieee std 1364-2001, less lines of code , more readable.

module project2(   output reg  q3, q2, q1, q0,   input  wire w,    output wire z0, z1,   input  wire clk, rst, enable ); 

also note missing driver on k3 , give problems jk_ff y3

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citation update:

from ieee std 1364-2001 section 12.3.3, , repeated in ieee std 1364-2005 section 12.3.3 , ieee std 1800-2012 section 23.2.2.1:

"if port declaration not include net or variable type, port can again declared in net or variable declaration."